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NXP Semiconductors /LPC800 /SYSCON /STARTERP0

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Interpret as STARTERP0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)PINT0 0 (DISABLED)PINT1 0 (DISABLED)PINT2 0 (DISABLED)PINT3 0 (DISABLED)PINT4 0 (DISABLED)PINT5 0 (DISABLED)PINT6 0 (DISABLED)PINT7 0RESERVED

PINT2=DISABLED, PINT4=DISABLED, PINT0=DISABLED, PINT3=DISABLED, PINT1=DISABLED, PINT6=DISABLED, PINT7=DISABLED, PINT5=DISABLED

Description

Start logic 0 pin wake-up enable register

Fields

PINT0

GPIO pin interrupt 0 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT1

GPIO pin interrupt 1 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT2

GPIO pin interrupt 2 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT3

GPIO pin interrupt 3 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT4

GPIO pin interrupt 4 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT5

GPIO pin interrupt 5 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT6

GPIO pin interrupt 6 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
PINT7

GPIO pin interrupt 7 wake-up

0 (DISABLED): Disabled

1 (ENABLED): Enabled
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data